Work

Selected professional experience and projects. The first three have full write-ups, followed by smaller projects. My accelerator-memory research is on the research page.

Smaller projects

Verilog · January 2026

Gate-level 32-bit ALU

A 32-bit ALU built only from gate primitives: AND, OR, add, subtract, set-less-than, and logical and arithmetic shifts, with zero, negative and overflow flags. The adder is two 16-bit carry-lookahead blocks (each made of 4-bit lookahead groups) with the carry passed between the halves, and the shifter is a five-stage mux network that reverses the bits for left shifts. A self-checking testbench compares every result and flag against a behavioral model over 24 directed and 50 random cases.

Source on GitHub

SystemVerilog · CS 1410 lab · fall 2025

Multicycle MIPS CPU

A 32-bit multicycle MIPS processor for CS 1410’s processor lab: a 15-state control FSM, a register file, and a datapath with PC, IR, MDR, A, B and ALUOut registers. It decodes 22 instructions (R-type arithmetic, logic and shifts, immediates, loads and stores, beq/bne, j, jal and jr) and runs on the XEM7310, with its memory loaded and read back over FrontPanel. The core runs from a divided clock of about 10 MHz.

Hand-drawn multicycle MIPS datapath on grid paper: PC, instruction and data memory, instruction register, register file, sign and zero extension, ALU source multiplexers, ALU, ALUOut register and PC source multiplexer, with a boxed branch-control circuit that ORs PCWrite with beq AND zero and bne AND not-zero.
My datapath sketch for the lab. The boxed circuit is the branch-control change for bne: the PC is written when PCWrite is set, when beq and the zero flag are both true, or when bne is true and the zero flag isn't.
LTspice schematic with two log-antilog multiplier transmitters built from op-amps and diodes, a summing and gain stage, an AM radio link model, and receive-side LC low-pass and high-pass filters.
Transmit side: two log–antilog multipliers, the summing and gain stage, the link model, and the receive-side LC filters.
LTspice schematic of two receiver channels, each with a diode, a 1 nF capacitor and 6.8 kilohm resistor envelope detector, a buffer, a 1.6 kilohm and 1 nF low-pass filter, and a buffer driving a 10 ohm speaker.
Receive side: envelope detection, filtering and a buffered output for each channel.

Proteus · Harvard Undergraduate Robotics Club

Battery monitor for the rover

A battery-monitor design for the robotics club’s University Rover Challenge rover. An Arduino Nano Every reads pack current and bus voltage from an INA219 over I²C for coulomb counting, temperature from a DS18B20 on a one-wire bus, and the pack voltage through a 220 kΩ / 10 kΩ divider (a 40 V pack reads about 1.74 V at the pin). An LM2596 buck regulator makes the 5 V rail from the pack.

Proteus schematic of a 40 volt battery, an LM2596 5 volt buck regulator, an Arduino Nano Every, an INA219 current monitor in series with a 10 ohm load, a DS18B20 temperature sensor, and a 220 kilohm and 10 kilohm divider into analog input A0.
The simulation schematic, with a 10 Ω load standing in for the rover.