Computer ArchitectureResearchHardware
Breaking the Memory Wall: 333-eDRAM in Tensor Accelerators
A computer-architecture study of dense embedded DRAM for energy-efficient transformer accelerators
A computer-architecture study asking whether a new embedded DRAM — 333-eDRAM (IGZO + CNFET + CMOS) — can break the memory-wall bottleneck in a TPU v4-inspired tensor accelerator running GPT-style attention. Using AccelForge, I modeled four memory configurations (all-SRAM baseline, local-buffer eDRAM, global-buffer eDRAM, and all-eDRAM) and analyzed how energy and reuse change with sequence length and einsum fusion. The finding: 333-eDRAM pays off most when used selectively in the global buffer, where its density keeps large attention intermediates on-chip — cutting energy by up to 16.4% with near-flat latency.
Computer ArchitectureAccelForgeTPU v4eDRAMMemory Hierarchy
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